Understanding Register Map Revisions

The latest airhdl update adds register map revisions, an important feature for checking the consistency of generated files like C headers and VHDL/SystemVerilog components.

Each register map now has a revision number, which airhdl manages internally. When you create a new register map, its revision number is initialized to zero. Then, every time you change anything in that register map (e.g. a register or a field), the revision number is automatically incremented.

You can see a register map’s current revision number in the register map view:

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The revision number also appears in the header of every generated file. Thus, you now have an easy way to check that your generated files all correspond to the same register map revision. Just compare the numbers in the headers.

Here’s what it looks like in the VHDL header:

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Even better, it’s possible to automate that consistency check, i.e. have the C driver check that it uses the same register map revision as the VHDL/SystemVerilog register component it is talking to.

For that, C headers now have a new symbol called
<REGISTER_MAP-NAME>_REVISION, for example:

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We’ve also added that constant to the VHDL and SystemVerilog packages, which makes it really easy to create a read-only “Revision” register that returns the value of the revision number.

All you have to do is create a “value” field in that register and drive the corresponding input port using the constant mentioned above. That way, the C driver can read the register, and compare its value with the revision number it sees in the C header. In case they don’t match, you have an inconsistency between the register definitions in the C header and the actual implementation in the RTL code.

Here’s how you would map the revision number constant to a field called “value” in a register called “reg_revision”:

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Enjoy!

Published by

Guy Eschemann

FPGA consultant

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