Amazon F1 Register File Creation with airhdl

Here’s a short video showing how you can use airhdl to quickly generate a SystemVerilog AXI4-Lite register file for use in your Amazon F1 Custom Logic (CL).

There’s nothing to install or license. Just register for free to airhdl, create your register map in the browser, and download the generated SystemVerilog module. Does it get any simpler than that?

Published by

Guy Eschemann

FPGA consultant

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