Category: Tools

Shiny and New: the SPI to AXI4-Lite Bridge

Following a user request, we have created an open-source SPI to AXI4-Lite bridge which allows you to access register banks generated by airhdl.com from any microcontroller over a Serial Peripheral Interface (SPI).

SPI to AXI4-Lite Bridge

The bridge is available in both VHDL and SystemVerilog versions, and comes as a single, self-contained file with no additional dependencies. It supports all four combinations of SPI clock phases and polarities, also known as SPI modes.

The source-code repository includes a VHDL testbench that was developed using the Open-Source VHDL Verification Methodology (OSVVM). The simulation requires a VHDL-2008 capable simulator such as Aldec Riviera-Pro.

We are releasing the SPI to AXI4-Lite bridge under a permissive Apache License 2.0, which allows you to use it in commercial applications.

Please feel free to try it out and let us know what you think!

Our List of VHDL, Verilog and SystemVerilog Lint Tools

Last update: August 2022

Over the years, we’ve been looking at a number of tools to check the quality of the generated code for our web-based AXI4 register generator. Here’s a compiled list of what we have found so far. Not all tools listed below are pure linters: some are HDL editors/IDEs, others are simulators with linting capabilities. The tools are listed in alphabetical order:

Aldec ALINT-PRO

AMIQ DVT Eclipse IDE, an Eclipse-based HDL editor with linting capabilities. The same company provides a SystemVerilog Testbench Linter called Verissimo.

BluePearl Analyze RTL

GHDL, a free VHDL simulator (using the -s switch).

HDL Works HDL Companion.

Siemens EDA HDL Designer has a built-in DesignChecker tool.

Mentor Graphics Questa CDC, a tool for clock-domain crossing verification.

Real Intent Ascent

Sigasi Studio, an Eclipse-based HDL editor, has built-in linting checks such as incomplete sensitivity lists and dead code detection.

Siemens EDA Questa Lint

slang, a software library that provides various components for lexing, parsing, type checking, and elaborating SystemVerilog code.

svlint, an open-source SystemVerilog linter.

Synopsys SpyGlass

TerosHDL, an open-source IDE with code linting capabilities.

Verible has a SystemVerilog style linter (verible-verilog-lint).

Verific INVIO, a framework for building custom EDA tools.

Verilator, a free Verilog simulator has built-in linting checks.

VHDL Style Guide (VSG), a tool for enforcing VHDL coding styles.

VHDL-Tool, a VHDL syntax checking, type checking and linting tool.

Xilinx Vivado Design Suite has a lot of built-in DRCs including clock-domain crossings.

Know a tool that’s not in this list? Please let us know.