FPGA/HDL Lint Tools

Every now and then in my FPGA consulting and coaching work I get asked about available FPGA lint tools. Here’s my current list, which I have compiled with the help of my twitter followers.

Please note that not all tools listed below are pure linters: some are HDL editors/IDEs, others are simulators with linting capabilities. The tools are listed in alphabetical order:

Aldec ALINT

AMIQ DVT Eclipse IDE, an Eclipse-based HDL editor with linting capabilities. The same company provides a SystemVerilog Testbench Linter called Verissimo

BluePearl Analyze RTL

GHDL, a free VHDL simulator (using the -s switch)

HDL Works HDL Companion

Invionics Invio, a framework for building custom EDA tools

Mentor Graphics HDL Designer has a built-in DesignChecker tool

Mentor Graphics Questa CDC, a tool for clock-domain crossing verification

Real Intent Ascent

Sigasi Studio, an Eclipse-based HDL editor, has built-in linting checks such as sensitivity lists and dead code

Synopsys SpyGlass

Verilator, a free Verilog simulator has built-in linting checks

VHDL-Tool, a VHDL syntax checking, type checking and linting tool.

Xilinx Vivado Design Suite has a lot of built-in DRCs including clock-domain crossings