Please note that not all tools listed below are pure linters: some are HDL editors/IDEs, others are simulators with linting capabilities. The tools are listed in alphabetical order:
GHDL, a free VHDL simulator (using the -s switch)
HDL Works HDL Companion
Invionics Invio, a framework for building custom EDA tools
Mentor Graphics HDL Designer has a built-in DesignChecker tool
Mentor Graphics Questa CDC, a tool for clock-domain crossing verification
Sigasi Studio, an Eclipse-based HDL editor, has built-in linting checks such as sensitivity lists and dead code
Verilator, a free Verilog simulator has built-in linting checks
VHDL-Tool, a VHDL syntax checking, type checking and linting tool.
Xilinx Vivado Design Suite has a lot of built-in DRCs including clock-domain crossings
Using a tool that’s not in this list? Please leave a comment or drop me a note.
Update #1 (08-FEB-2017): added AMIQ tools, as suggested by Tomasz Hemperek
Update #2 (26-AUG-2018): added VHDL-Tool as suggested by Mike
Update #3 (28-MAY-2019): added Mentor Graphics HDL Designer and Questa CDC as suggested by Waleed