Last update: August 2022
Over the years, we’ve been looking at a number of tools to check the quality of the generated code for our web-based AXI4 register generator. Here’s a compiled list of what we have found so far. Not all tools listed below are pure linters: some are HDL editors/IDEs, others are simulators with linting capabilities. The tools are listed in alphabetical order:
GHDL, a free VHDL simulator (using the -s switch).
HDL Works HDL Companion.
Siemens EDA HDL Designer has a built-in DesignChecker tool.
Mentor Graphics Questa CDC, a tool for clock-domain crossing verification.
Sigasi Studio, an Eclipse-based HDL editor, has built-in linting checks such as incomplete sensitivity lists and dead code detection.
slang, a software library that provides various components for lexing, parsing, type checking, and elaborating SystemVerilog code.
svlint, an open-source SystemVerilog linter.
TerosHDL, an open-source IDE with code linting capabilities.
Verible has a SystemVerilog style linter (
Verific INVIO, a framework for building custom EDA tools.
Verilator, a free Verilog simulator has built-in linting checks.
VHDL Style Guide (VSG), a tool for enforcing VHDL coding styles.
VHDL-Tool, a VHDL syntax checking, type checking and linting tool.
Xilinx Vivado Design Suite has a lot of built-in DRCs including clock-domain crossings.
Know a tool that’s not in this list? Please let us know.