📄️ How to use an airhdl Register Bank in a Xilinx Vivado Project
To use an airhdl-generated AXI4-Lite register bank in a Xilinx Vivado project, you can either add the register bank as a module in a block design, or instantiate it in the RTL code.
📄️ How to use an airhdl register bank in a Xilinx Platform Studio (XPS) project
This article describes how to integrate an airhdl-generated register component into a Xilinx Platform Studio (XPS) project.