Register Management Done Right

Managing register banks in modern FPGA or SoC projects is both a tedious and an error-prone task. Creating the implementation and documentation files by hand is a recipe for disaster as it is almost guaranteed that your files will go out of sync at some point during the course of the project. In addition to that, very few design teams actually take the time to write comprehensive testbenches to verify their register bank logic.

By leveraging the power of code generation and web-based applications, airhdl offers a fresh and easy-to-use solution to your register bank management needs. Creating a register map in airhdl is just a matter of opening a web browser, logging in to airhdl, and entering the register definitions in an easy-to-use graphical user interface.

Register maps that you have created in airhdl can be shared between team members such as hardware designers and software developers for easy collaboration. Comprehensive built-in design rule checks, which are executed automatically before any code generation, ensure that your register map does not contain any errors such as invalid identifiers, overlapping registers or fields, and a number of other issues.

The download button gives you immediate access to the generated files for your register map:

  • C/C++ header

  • SystemVerilog RTL (module and package)

  • SystemVerilog testbench

  • VHDL RTL (component and package)

  • VHDL testbench

  • HTML documentation

  • Markdown documentation


  • JSON object

Behind the scenes, airhdl keeps track of the changes to your register maps. Every time a register map is updated, airhdl automatically increments the register map’s revision number. As that revision number is available in every generated file, it is very easy to check that local files (e.g. C header and RTL component) actually correspond to the same register map revision.

Welcome to a new EDA experience!