How to add an airhdl register file to a Xilinx ZYNQ System

Here’s a short video showing how you can use airhdl to quickly create an AXI4-Lite register file, and integrate the generated component into an existing Xilinx ZYNQ System using the Vivado block diagram editor.

Published by

Guy Eschemann

FPGA consultant

Leave a Reply

Your email address will not be published. Required fields are marked *